The present invention relates to a semiconductor device and a manufacturing technique for the same. Particularly, the present invention is concerned with a technique applicable effectively to a semiconductor device having a non-volatile memory and a method of manufacturing the same.
Electrically erasable programmable non-volatile memories such as EEPROM (Electrically Erasable Programmable Read Only Memory) and flash memory permit onboard rewriting of programs, thus permitting shortening of the development period and improvement of the development efficiency. Therefore, the application thereof is spreading to various uses, including the use in multifarious small-lot production, tuning by destinations, and program updating after shipping.
As an electrically erasable programmable non-volatile memory there mainly is used EEPROM using the ordinary polysilicon as a floating electrode. Recently, attention has been paid to an MNOS (Metal Nitride Oxide Semiconductor) structure using a nitride film (silicon nitride (e.g. Si3N4)) as a charge storage layer or an MONOS (Metal Oxide Nitride Oxide Semiconductor) structure. In this case, the electric charge which contributes to the storage of data is accumulated in a discrete trap of a nitride film which is an insulator, so that even if there occurs a defect in any part of an oxide film which surrounds an accumulation node, with consequent occurrence of abnormal leakage, there is no fear of complete removal of the electric charge on the charge storage layer. Thus, it is possible to improve the data holding reliability.
In connection with the configuration of a memory cell there has been proposed a memory cell of a single transistor structure. As a write/erase method there has been proposed not only a method wherein write is performed by full surface FN (Fowler Nordheim) tunneling injection from a semiconductor substrate and erasing is performed by FN tunneling current to the semiconductor substrate, but also a method wherein erasing is performed by FN tunneling current to a semiconductor substrate or to the source and drain regions. Further, in the case of a MONOS type single transistor cell structure, it is apt to be influenced by disturb in comparison with the EEPROM cell structure. In view of this point there also has been proposed a split gate type memory cell structure of a two-transistor configuration provided with a control gate electrode.
As to the split gate type memory cell of such a two-transistor configuration, a description is found in for example Japanese patent laid-open No. 2004-266203 (see Patent Literature 1). In Patent Literature 1 is disclosed a non-volatile memory cell configuration having a first electrode formed on a semiconductor substrate via a gate insulating film for charge storage, a second gate electrode formed on the semiconductor substrate via a gate insulating film in adjacency to the first gate electrode, and semiconductor regions for source and drain formed on both-side semiconductor substrate portions in the direction of arrangement of the first and second gate electrodes.
Moreover, for example in Japanese patent laid-open No. 2002-198523 (see Patent Literature 2) there is disclosed a technique of forming semiconductor regions for source and drain using as a mask a first side wall formed on a side wall of a gate electrode of MISFET, then forming a second side wall on a side wall of the first side wall and, using the second side wall as a mask, forming a silicide layer on each of the semiconductor regions for source and drain.
Further, for example in paragraphs [0050] and [0051] of Japanese patent laid-open No. 2004-079893 (see Patent Literature 3) there is disclosed a technique wherein, at the time of forming a side wall on a side face of a gate electrode, a pattern of an insulating film permitting exposure of a contact region of a polysilicon resistor is formed on the polysilicon resistor with use of an insulating film for forming the side wall.
[Patent Literature 1]                Japanese patent laid-open No. 2004-266203        
[Patent Literature 2]                Japanese patent laid-open No. 2002-198523        
[Patent Literature 3]                Japanese patent laid-open No. 2004-079893 (paragraphs [0050] and [0051])        